1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly, to a semiconductor storage device comprising an Error Checking and Correcting (ECC) circuit.
2. Description of the Related Art
In recent years, as semiconductor manufacturing techniques have been advanced, devices have been increasingly miniaturized. For example, the packaging density of a semiconductor storage device, such as representatively a dynamic random access memory (hereinafter referred to as a DRAM) or a static random access memory (hereinafter referred to as an SRAM), has been improved.
A redundant relief technique is generally known in which a defective memory cell is replaced with a spare memory cell in order to improve the yield of a DRAM or an SRAM. However, the redundant relief technique cannot overcome a defect occurring due to a deterioration in characteristics of an element during use or a defect occurring due to a soft error by an alpha ray or a cosmic ray, which are involved with miniaturization of elements, such as memory cells, sense amplifiers and the like. Such a problem with reliability is solved by a known self-correction technique using an ECC circuit.
Although a system is conventionally implemented on a plurality of chips, the increase of packaging density due to miniaturization has led to an increase in demand for System-On-Chips (SOCs) where a DRAM or an SRAM and a logic circuit or a CPU are provided together on a single chip. SOCs are characterized in that the width of a bus for a memory provided thereof can be relatively arbitrarily set, and a considerably wide bus arrangement (e.g., 256 bits) can be used for a general-purpose discrete memory. By using such a wide bus arrangement, performance can be significantly improved, such as a significant improvement in a data transfer rate between a CPU and a memory, or the like.
For example, U.S. Pat. No. 5,384,789 discloses a semiconductor storage device with an ECC function which comprises a set of cell arrays and sense amplifiers, several blocks of data bus amplifiers and data write amplifiers, a syndrome generating circuit, and an error correcting circuit, wherein each block has a syndrome decoding circuit for decoding a syndrome generated by the syndrome generating circuit, thereby reducing the number of wiring lines. U.S. Pat. No. 7,237,175 discloses an example in which a plurality of ECC circuits are used to perform error checking and correction and data is arranged so as not to be adjacent to each other in ECC processing units, thereby avoiding a multi-bit error during occurrence of a soft error.
US Patent Application Publication No. 2007/0038919 discloses an example in which an ECC process is performed using a large bit width, wherein an ECC circuit is provided adjacent to a sense amplifier array of a DRAM, which is effective to a multi-bit process.
Japanese Patent Application Publication No. S62-248198 discloses an example in which vertical and horizontal parity codes are used to control selection switching of a horizontal group and a vertical group so that each of a plurality of physically neighboring memory cells and check cells that are grouped in units corresponding to the number of bits included in the horizontal group or the vertical group does not belong to the same horizontal group or the same vertical group, whereby horizontal group parity check and vertical group parity check can be achieved using a totally similar circuit arrangement.